1. Field of the Invention
The present invention relates to a consumed power saving memory control circuit, and more specifically to a power saving memory control circuit reducing a consumed power of a memory.
2. Description of Related Art
For example, some memory control circuit has been composed of one bank which is connected to a 64-bit memory data bus. Considering this memory control circuit in units of bank, as shown in FIG. 1, the memory control circuit includes a memory controller 100 coupled through a 64-bit memory data bus MD&lt;63-0&gt; to a memory 102 composed of dynamic random access memories DRAM0 to DRAM7, which constitute one bank. The memory controller 100 is configured to access the memory 102 by use of a row address strobe signal RAS, a column address strobe signal CAS&lt;7-0&gt;, a write enable signal WE and a memory address MA. Here, the row address strobe signal RAS is supplied in common to all DRAM0 to DRAM7 included in the one bank.
In order to access the memory in the shown prior art memory control circuit, first, the row address strobe signal RAS is activated, so that a plurality of data on a plurality of rows corresponding to a strobed row address are read out and transferred to a corresponding number of row buffers (each called a "sense amplifier"). Thereafter, the column address strobe signal CAS is activated so that one data is selected from a plurality of data outputted from the plurality of sense amplifiers, and then, outputted through an output amplifier.
In this operation, when the row address strobe signal RAS is inactivate, a RAS related internal circuit is precharged, and, when the column address strobe signal CAS is inactivate, the CAS related internal circuit is precharged. When the row address strobe signal RAS is activated, the RAS related internal circuit is discharged as a result of the data reading, and when the column address strobe signal CAS is activated, the CAS related internal circuit is discharged as a result of the read-out data outputting. Therefore, by repeating activation and deactivation of the row address strobe signal RAS, each DRAM consumes an electric power.
In the prior art memory control circuit, however, since the row address strobe signal RAS is in common to all DRAMs included within the same bank, when the memory is accessed either in units of one byte or in units of one word which is smaller than the width of the memory data bus, the row address strobe signal RAS supplied to DRAMs other than the DRAM(s) to be accessed, are also activated. This results in an increased consumed electric power.